An active matrix type display device selects pixel circuits arranged in a two dimensional manner on a row basis and writes voltages in the selected pixel circuits in accordance with display data to display an image. In order to select pixel circuits on a row basis, a shift register is used as a scanning signal line drive circuit to sequentially shift an output signal based on a clock signal. In a display device performing dot sequential driving, moreover, a data signal line drive circuit includes a shift register which is similar to that described above.
In a liquid crystal display device and the like, occasionally, a drive circuit for pixel circuits is formed monolithically with the pixel circuits by a manufacturing process for forming TFTs (Thin Film Transistors) in the pixel circuits. In this case, preferably, the drive circuit including a shift register is formed by transistors which are equal in conduction type to the TFTs, in order to reduce manufacturing cost. Moreover, increase of clock signals to be supplied to the shift register causes increase of layout area and power consumption of clock interconnection, and the like. In consideration of such a circumstance, it is necessary to configure a shift register that operates based on two-phase clock signals, by use of transistors of an identical conduction type.
In a shift register configured with an N-channel type transistor, a bootstrap circuit shown in FIG. 36 is used for outputting a clock signal without changing a voltage level of the clock signal. In the circuit shown in FIG. 36, when an input signal IN turns into a high level, a node N1 is precharged to a voltage potential (VDD-Vth) (VDD: a power supply voltage, Vth: a threshold voltage of a transistor T1) and a transistor T2 turns into an On state. Thereafter, when the input signal IN turns into a low level, the node N1 turns into a floating state; however, the transistor T2 is maintained at the On state. In this state, when a clock signal CK changes from the low level to the high level, the voltage potential at the node N1 becomes higher than VDD by function of a capacitor C1 provided between a gate terminal and a source terminal of the transistor T2 (a bootstrap effect). Therefore, the clock signal CK having a maximum voltage of VDD passes through the transistor T2 without voltage drop, and then is output from an output terminal OUT without change of the voltage level thereof.
In order to configure a shift register for use in a display device and the like by use of the circuit shown in FIG. 36, it is necessary to add a function of discharging the node N1 and a function of pulling down the output signal OUT. With regard to this point, conventionally, there have been known the following techniques. As shown in FIG. 37, Patent Document 1 describes a configuration in that a transistor Q11 discharges a node N1, based on an output signal from a subsequent circuit, and a transistor Q12 pulls down an output signal OUT, based on a clock signal CK2. As shown in FIG. 38, Patent Document 2 describes a configuration in that a transistor Q21 discharges a node N1 and transistors Q22 and Q23 pull down an output signal OUT, based on an output signal CT from a subsequent circuit.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2001-273785
[Patent Document 2] Japanese Laid-Open Patent Publication No. 2002-258819